The present invention relates generally to random access memory (RAM) circuits. More specifically, but without limitation thereto, the present invention relates to a complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) cell in which the high storage node is driven above the voltage rail and the low storage node is driven below the ground rail during a read access.
In a conventional CMOS SRAM cell, microscopic intrinsic fluctuations in the channel region of minimum geometry cell MOSFETs become more pronounced for device generations below 130 nm. Macroscopic extrinsic variations in the cell due to process variations across chip, wafer and dice coupled with temperature and Vdd variations make the cell increasingly unstable with scaling. The higher cell instability that accompanies scaling requires larger beta ratios, which results in a larger cell, array, and chip area and consequently higher chip and system cost.
With down-scaling of device threshold voltages, increases in SRAM array size and percentage of chip transistors dedicated to SRAM, the total subthreshold leakage current from cell transistors increases, significantly increasing standby power dissipation from the SRAM array compared to peripheral circuitry and random logic cores. The increased standby power dissipation of the SRAM array imposes increasingly severe constraints on battery life and the size of portable equipment using conventional SRAM cells.
As SRAM array size increases, SRAM cell delay tends to improve less rapidly than logic gate delay. Higher cell drive may be achieved by boosting the word line voltage during cell access, but the resulting increase in cell drive is only marginal.
The present invention advantageously addresses the problems above as well as other problems by providing a source pulsed complementary metal oxide semiconductor static random access memory with higher cell stability, lower bit line delay, and lower standby power than previously available in low-voltage devices.
In one embodiment, the present invention may be characterized as a memory cell that includes a first pull-up device, a first pull-down device connected to the first pull-up device, a first cell access device connected to the first pull-down device, a second pull-up device connected to the first pull-up device, a second pull-down device connected to the second pull-up device, and a second cell access device connected to the second pull-down device wherein the first cell access device and the second cell access device are connected to a word line that is driven to a voltage that is less than Vss in standby mode and is pulsed to Vdd during read access.